The present invention relates to a method for forming a capacitor in a memory cell in a dynamic random access memory.
Requirements for improvements in the integration of dynamic random access memory including a large number of memory cells, each of which comprises a pair of a transistor and a capacitor, have increased. In order to satisfy this requirement, it is required to further reduce an occupying area of each unit cell. The reduction in occupying area of each unit cell further requires a reduction in a horizontal area of the capacitor in the unit memory cell.
On the other hand, a sufficiently large capacitance of the memory cell is also necessary to provide the memory cell with a sufficient resistivity to soft errors caused by noise charges which are generated by alpha particles. The capacitance of the memory cell is proportional to an area of a dielectric film sandwiched between top and bottom electrodes which constitute the capacitor in the unit memory cell. The increase in capacitance of the memory cell requires an increase in area of the dielectric film sandwiched between the top and bottom electrodes. As described above, it is also required to reduce the horizontal area of the capacitor.
In the above circumstances, the issue with a design for the capacitor in the unit memory cell is how to reduce the horizontal area of the capacitor and enlarge the area of the dielectric film of the capacitor. It was proposed to form a vertically extending bottom electrode, for example, a cylindrically shaped bottom electrode in order to increase in the area of the dielectric film between the top and bottom electrodes of the capacitor in the memory cell. This proposals are disclosed in the Japanese laid-open patent applications Nos. 3-214668, 4-99373, 4-264767, and 3-232271.
A typical conventional method for forming a capacitor with a cylindrically shaped bottom electrode in the unit memory cell in the dynamic random access memory device will be described with reference to FIGS. 1A-1H.
With reference to FIG. 1A, field oxide films 2 are selectively formed in a surface region of a semiconductor substrate 1 to define an active region. A gate oxide film and a gate electrode 5 are selectively formed on a channel region in the active region defined by the field oxide films 2. Source and drain regions 3 and 4 are selectively formed in the surface region of the semiconductor substrate 1 to sandwich the channel region under the gate electrode 5. A first inter-layer insulator 6 is formed on an entire surface of the device to embed the gate electrode 5. A bit line through hole is selectively formed in the first inter-layer insulator 6 so that the bit line through hole overlies the drain region 4. A bit line plug is formed within the bit line through hole to plug up the bit line through hole and further bit lines 7 are formed on the first inter-layer insulator 6. A second inter-layer insulator 8 is formed on an entire surface of the device to embed the bit lines 7. A silicon nitride film 10 is formed on the second inter-layer insulator 8. A photo-resist film 11 is formed on the silicon nitride film 10. The photo-resist film 11 is patterned to have an opening over the source region 3. The silicon nitride film 10 is formed with an opening which lies under the opening of the photo-resist film 11. The silicon nitride film 10 is used as a mask to form a contact hole 9, which penetrates through the second inter-layer insulator 8, the bit lines 7 and the first inter-layer insulator 6, over the source region 3 so that the surface of the source region 3 is partially exposed.
With reference to FIG. 1B, after removal of the photo-resist pattern 11, a first silicon film 12 is formed both on the silicon nitride film 10 and within the contact hole 9 to plug up the same. The first silicon film 12 is doped with an impurity to increase a conductivity thereof.
With reference to FIG. 1C, a silicon oxide film 14 is formed on the first silicon film 12 by a chemical vapor deposition method. A photo-resist film is formed on the silicon oxide film 14 and then patterned to form a photo-resist pattern 13 which overlies the silicon oxide film 14. The center of the photo-resist pattern 13 is aligned to the center of the contact hole. The horizontal size of the photo-resist pattern 13 is larger than the horizontal size of the contact hole.
With reference to FIG. 1D, the photo-resist pattern 13 is used as a mask to selectively etch the silicon oxide film 14 and the first silicon film 12 so that the silicon oxide film 14 and the first silicon film 12 remain only under the photo-resist pattern 13 and over the contact hole 9 and peripheral areas of the contact hole 9. Thereafter, the photo-resist pattern 13 is removed.
With reference to FIG. 1E, a second silicon film 15 having a thickness in the range of 100 nanometers to 200 nanometers is formed on an entire surface of the device to extend over the silicon nitride film 10 and on vertical side walls of the first silicon film 12 and the silicon oxide film 14 as well as on the top surface of the silicon oxide film 14. As a result, the silicon oxide film 14 is surrounded by the first and second silicon oxide films 12 and 15.
With reference to FIG. 1F, the second silicon film 15 is then subjected to an etch-back so as to leave only vertical portions of the second silicon film 15 extending on the vertical surfaces of the first silicon film 12 and the silicon oxide film 14.
With reference to FIG. 1G, the silicon oxide film 14 is etched by fluorine acid to thereby form a bottom electrode which comprises the vertical portions of the second silicon film 15 and the horizontal portion of the first silicon film 12.
With reference to FIG. 1H, a dielectric film 16 is formed on an entire surface of the device to extend on the silicon nitride film 10 and on outer vertical side wall of the second silicon film 15 of the bottom electrode as well as on the top of the second silicon film 15 and inner vertical side wall of the second silicon film 15, in addition the top of the first silicon film 12, to thereby cover an entire surface of the bottom electrode. A top electrode 17 is formed on an entire surface of the dielectric film 16, to thereby form a capacitor for the memory cell in the dynamic random access memory.
As described above, the conventional processes for forming the memory cell capacitor are complicated. The reasons for such complicated processes for forming the memory cell capacitor are as follows. First, it is difficult to define a fine pattern for the cylindrically shaped bottom electrode by use of the normal photo-lithography since the size of the fine pattern is smaller than a resolving power of the reduced exposure. Second, if an annular pattern is formed and subsequently an etching is carried out, then a disconnection from a contact plug will appear due to the etching process.
The above conventional processes for forming the memory cell capacitor are so complicated as to include two formations of the silicon films, two anisotropic dry etching processes, one wet etching process. Such complication of the processes for forming the memory cell capacitor of increases in the cost thereof and decrease the in yield of the products due to residue and particles generated by the etching processes.